Inductive storage capacitor

ABSTRACT

A device includes an element (e.g. in the shape of a sleeve) and a core located in an interior volume defined by the element and at least partially surrounded by the element. The element has two portions: one portion overlaps at least a region of the core thereby to form a capacitor, while another portion surrounds the core thereby to form an inductor. The device may further include an additional capacitor formed by another element that is separated from the core but overlaps at least a region of the core when viewed in a direction perpendicular to the core. The two elements substantially surround the core. The core may be used to hold charge in a non-volatile manner, even when no power is supplied to the device. The device can be manufactured in the normal manner, by forming a via hole, depositing a conductive layer in the via hole to form a sleeve-shaped element, forming a dielectric layer over the conductive layer so that the dielectric layer defines an interior volume, and filling the interior volume with a plug of conductive material that forms the core. An additional dielectric layer and an additional conductive layer may be formed to implement the additional capacitor.

BACKGROUND

[0001] A book entitled “Nonvolatile Semiconductor Memory Technology”,Edited by William D. Brown and Joe. E. Brewer and published by IEEEPress (1998), ISBN 0-7803-1173-6, states, on page 1 “The ultimatesolution—a genuine nonvolatile RAM that retains data without externalpower, can be read from or programmed like a static or dynamic RAM, andstill achieve high-speed, high-density, and low power consumptions at anacceptable cost—remains unfeasible to this day.” On page 6, this bookdescribes a class of nonvolatile memory devices that store a charge on aconducting or semiconducting layer (called “floating gate”) that iscompletely surrounded by dielectric and an opposing layer (called“control gate”) that together form a capacitor (commonly known as“storage capacitor”).

[0002] An article entitled “Applied Materials Introduces New StorageCapacitor Solution for Gigabit DRAMs” dated Jul. 8, 1998 describes useof tantalum pentoxide (Ta2O5) to form storage capacitors in memorydevices. Such a storage capacitor cannot hold its charge over anextended period of time and loses a stored data bit unless its charge isrefreshed periodically, as described athttp://www.ee.cooper.edu/courses/course_pages/past_courses/EE151/MEMS_HO1/. As described therein, the periodicrefreshing requires additional memory circuitry and complicates theoperation of dynamic random access memory (DRAM) formed from suchcapacitors.

[0003] The above-described periodic refreshing can be avoided by flashmemory. There are several kinds of flash memory, including asingle-transistor cell and a two-transistor cell as described in anarticle in Electronic Design, dated Aug. 9, 1999, and entitled“Feature-Rich Flash Memories Deliver High Density” by Dave Bursky. Asdescribed therein, a single-transistor cell is employed in a NOR-likelogic structure to form a random-access storage array (called “flashEPROM”). Moreover, the two-transistor (or a merged transistor,dual-gate) cell is also a NOR-style configuration (called “flashEEPROM”). On-chip decoding circuits divide an array of two-transistorcells into small blocks (256 bytes to 4 kbytes) that normally enable asmaller portion of the chip to be erased and reprogrammed.

[0004] Several issues exist with the flash memory as described in theabove-identified book by Brown and Brewer, such as slow trapping,polarization, oxide breakdown/leakage, hot-electron injection, andoxide-hopping conduction, as described in Table 6.2 on page 362

SUMMARY

[0005] In accordance with the invention, a semiconductor substrate hasformed therein an inductor and a capacitor integrated into a singledevice (called an “inductive capacitor”). The inductor causes thecapacitor to charge faster than the charging of a prior art device thathas significant capacitance but negligible inductance (e.g. a device inwhich the capacitive contribution to the resonant frequency (of an LCcircuit formed by such a prior art device) is greater than 90% of theinductive contribution). The device can include any structure thatimplements the inductive and capacitive functions in an integratedmanner. Such a device having a significant inductive effect can be usedin any radio-frequency (RF) circuit.

[0006] In one embodiment, the device includes a rod-shaped secondelement (hereinafter simply “plug”) that is located in an interior spacedefined by a sleeve-shaped first element (hereinafter simply “sleeve”),thereby to form a capacitor (also called “first capacitor”) and aninductor in the same device. The core is separated from the sleeve by adielectric material (also called “trap material”) that stores anelectrical charge when the device is powered off (such assilicon—silicon dioxide interface). An inductive capacitor that includesa trap material between the two elements is also referred to as an“inductive storage capacitor.” Such an inductive storage capacitor isused to implement a nonvolatile memory cell in one application, and atiming circuit in another application.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007]FIG. 1 illustrates in integrated circuit die containing aninductive capacitor in one embodiment of the invention.

[0008]FIG. 2 illustrates flux lines induced in the inductive capacitorof FIG. 1 during operation.

[0009]FIGS. 3 and 5 illustrate, in circuit diagrams, the inductivecapacitor of FIG. 1 filled with a trap material, and coupled to avoltage source and a sensor, in two embodiments.

[0010]FIG. 4 illustrates physical structure of one embodiment thatintegrates an inductive capacitor with a sense capacitor, by use of anadditional element.

[0011]FIG. 6 illustrates a symbol for the inductive capacitor.

[0012]FIG. 7 illustrates electron flow on an outer surface of theinductive capacitor of FIG. 1.

[0013]FIG. 8 illustrates an inductive capacitor that does not holdcharge when powered down.

[0014]FIG. 9 illustrates a cross section of the inductive storagecapacitor.

[0015]FIG. 10 illustrates the cross section of FIG. 9 with superimposedthereon symbols of the circuit elements formed by the structure.

[0016]FIG. 11 illustrates, in an enlarged view, an interface formedbetween layers 192 and 193 causing the electrons to be stored under theinfluence of an inductive field.

[0017]FIG. 12 illustrates the crystal structure of the silicon—silicondioxide interface where free electrons are trapped in electrons holes.

[0018] FIGS. 13-20 illustrates, in a cross sectional view, formation ofvarious layers in a via hole of a silicon wafer.

[0019]FIG. 21 illustrates a plan view of the inductive storage capacitorstructure illustrated in FIG. 20, along the direction A-A. via hole onthe silicon wafer.

[0020]FIG. 22 illustrates a timing diagram for reading a dischargedstate and writing a charged state.

[0021]FIG. 23 illustrates a timing diagram for reading a charged stateand writing a one state.

[0022]FIG. 24 illustrates a timing diagram for reading a dischargedstate and writing a discharged state.

[0023]FIG. 25 illustrates a timing diagram for reading a charged stateand writing a discharged state.

[0024]FIGS. 26A, 26B, and 27-29 illustrate, in cross-sectionional views,various embodiments of an inductive storage capacitor in an upside downconfiguration relative to FIG. 9.

[0025]FIG. 30 illustrates a cross section of the inductive storagecapacitor with another material deposited into the floating element.

[0026]FIG. 31 illustrates, in a block diagram, use of an inductivestorage capacitor as a storage element.

[0027]FIG. 32 illustrates, in a circuit diagram, circuit elements thatrealize the embodiment of FIG. 31.

[0028]FIG. 33 illustrates a memory cell array formed of inductivestorage capacitors.

DETAILED DESCRIPTION

[0029] A semiconductor substrate 1 (FIG. 1) in one embodiment has formedtherein a device 2 including a first element 3 of a conductive materialthat surrounds a second element 4 that may be of the same or differentconductive material. Depending on the aspect ratio, the second element 4can be in the shape of a coin (that has a height significantly smallerthan the diameter, e.g. an order of magnitude smaller), or a needle(that has a height significantly larger than the diameter, e.g. an orderof magnitude larger), or a rod (which has an aspect ratio somewherebetween a coin and a needle).

[0030] As would be apparent to the skilled artisan, a ring-shaped firstelement 3 surrounding a coin-shaped second element 4 has a negligiblecapacitive effect and significant inductive effect (e.g. the capacitivecontribution to the resonant frequency (of an LC circuit formed by sucha device) is less than 10% of the inductive contribution). Such a device2 having a significant inductive effect can be used in anyradio-frequency (RF) circuit. Another device 2 having significantinductive as well as capacitive effects can be used as a storagecapacitor for nonvolatile memory, as described herein. Although aspecific structure is illustrated in FIG. 1, device 2 can include anystructure that implements the inductive and capacitive functions in anintegrated manner.

[0031] In one embodiment, the device 2 includes a rod-shaped secondelement 4 (hereinafter simply “plug”) that is located in an interiorspace defined by a sleeve-shaped first element 3 (hereinafter simply“sleeve”), thereby to form a capacitor (also called “first capacitor”)and an inductor in the same device. A trace (not shown in FIG. 1) isattached to an input terminal 24 (FIG. 2) located at one end of sleeve3, to provide current and voltage for operation of the device. Asdescribed below, the inductor causes the capacitor to charge faster thanthe charging of a prior art device that has significant capacitance butnegligible inductance (e.g. the capacitive contribution to the resonantfrequency (of an LC circuit formed by such a prior art device) isgreater than 90% of the inductive contribution).

[0032] Plug 4 is separated from sleeve 3 by any dielectric material,including, for example a material 5 (also called “trap material”) thatstores an electrical charge when device 2 is powered off (such as eithersilicon—silicon dioxide interface, or silicon—silicon nitrideinterface). An inductive capacitor that includes a trap material 5between sleeve 3 and plug 4 is also referred to as an “inductive storagecapacitor.”

[0033] Sleeve 3 can have any cross-section, such as circular,rectangular, triangular, etc. Moreover, the sleeve need not becontinuous in the cross-sectional view (e.g. such a sleeve may have across-section in the shape of the letter “C” of the English alphabet).One end of sleeve 3 is coupled to a voltage source, so that duringoperation electrons flow into the device from this end of the sleevetowards the other end, thereby to form an inductor (device in which anelectromotive force is induced in it or in a nearby circuit by a changeof current in either itself or the nearby circuit). Plug 4 can also haveany cross-section, which may or may not be solid, depending on theembodiment.

[0034] During operation, an inductive field 23 (FIG. 2) is generatedbetween an inner surface 21 of sleeve 3 (which acts as a coil) and asurface 22 of plug 4 (which acts as a core). Surfaces 21 and 22 togetherform a capacitor 29. Inductive field 23 is used to store a charge intrap material 27 that is located between surfaces 21 and 22. Ascapacitor 29 charges, inductive field 23 is formed, and causes electronwave movement (a well known phenomenon in physics, as described inChapter 4 entitled “Physical Aspects of Cell operation and reliability”in the book entitled “Flash Memories” by Paolo Cappelletti et al. KluwerAcademic Publishers, 1999, which chapter is incorporated by referenceherein in its entirety) or tunneling to occur through trap material 27(e.g. along the silicon—silicon dioxide interface).

[0035] As capacitor 29 (also called “storage capacitor”) reaches thelevel of the voltage supply, inductive field 23 collapses causing freeelectrons to be trapped in the silicon—silicon dioxide interface.Therefore, ‘trap to band tunneling’ (well known in the art) is performedby creation and collapse of inductive field 23. The process is reversedwhen storage capacitor 29 is discharged, and the inductive field 23 isreversed causing the trapped electrons to be removed. Such an inductivestorage capacitor 20 is of a different design than a storage capacitorin conventional non-volatile solid state memory devices known toapplicant, and uses a new method for programming and reading the levelsof the electrons that are stored in the device.

[0036] Inductive storage capacitor 20 (FIG. 2) forms an electricalcircuit 30 (FIG. 3) that in turn can be implemented in other structuresapparent to the skilled artisan in view of the disclosure. Circuit 30includes a capacitor 33, an inductor 34 coupled in parallel to capacitor33, and a trap material 37 located inside capacitor 33. In oneembodiment, inductor 34 is in contact with trap material 37. However,inductor 34 need not be in contact with, e.g. can be simply adjacent totrap material 37 (if there is another material located therebetween).

[0037] Regardless of the relative locations of inductor 34 and trapmaterial 37, during operation of circuit 30, inductor 34 generates afield (e.g. similar or identical to field 23 discussed above inreference to FIG. 2) passing through trap material 37. In thisembodiment, a sensor 36 is coupled to capacitor 33, to sense a chargestored in the traps of trap material 37. In one implementation,capacitor 33, inductor 34, sensor 36 and voltage source 31 are allcoupled to a common terminal 32 as illustrated in FIG. 3 although inother embodiments, other such couplings may be made.

[0038] In one embodiment, an inductive storage capacitor 20 (FIG. 4) islocated adjacent to an element 45 to form a device 40 wherein a surface46 of element 45 and a surface 44 of plug 4 form a capacitor (called“sense capacitor”) 48. Sensing capacitor 48 is separate and distinctfrom (but coupled in series to) the above-discussed capacitor 29 (FIGS.2 and 4) in inductive storage capacitor 20. As trap material 27 becomesfilled with electrons, a surface 44 of plug 4 collects an opposite (i.e.negative) charge and the voltage level of adjacent element 45 (orsensing capacitor) is changed. The voltage level (on sensing capacitor48) and current flow (through sensing capacitor 48) is used to detectthe current state of the storage capacitor.

[0039] Device 40 (FIG. 4) forms an electrical circuit 50 (FIG. 5) thatcan also be implemented in other structures apparent to the skilledartisan in view of the disclosure. Circuit 50 is similar or identical tocircuit 30 described above except for the following differences. Circuit50 includes an additional capacitor 55 (also called “sense capacitor”)in series with capacitor 33 (also called “storage capacitor” anddescribed above in reference to FIG. 3). Note that inductor 34 iscoupled in parallel to storage capacitor 33 (and in series with sensecapacitor 55). Circuit 50 also includes a sensor 56 that is coupled to aterminal of sensor capacitor 55. Although there is no sensor coupled tostorage capacitor 33 in this embodiment, a voltage source 31 is coupledto a terminal 32 (of capacitor 33) that in turn is coupled to inductor34. Note that trap material 37 is not present inside sense capacitor 55,instead a dielectric material may be present.

[0040] When voltage source 31 (FIG. 5) is coupled to terminal 32 thevoltage potential causes current to charge storage capacitor 33 and inparallel induce an inductive field in the inductor 34. As voltage source31 is applied current flows from storage capacitor 33 to sense capacitor55 causing sense capacitor 55 to charge. The delay in charging sensecapacitor 55 is measured by connecting sense capacitor 55 to a sensor 56to measure the voltage or current on the output of sense capacitor 55.Such delay is different, depending at least on whether or not trapmaterial 37 holds a charge therein. Therefore, sensing the delay readsthe data stored in device 50.

[0041] The inductance, capacitance and density of state (the number ofavailable electron states per unit volume and energy) of circuitelements 33, 55, 34 and 37 in circuit 50 (FIG. 4) affect the delay (andtherefore the speed of operation) of circuit 50. Depending on theapplication, values for such parameters may be different from the valuesdescribed below in reference to FIGS. 13-20. Such parameters can becalculated as follows. The capacitance of each of capacitors 33 and 55by themselves is calculated, in ferries, by using a simple parallelplate model of the type well known in the art. For example, one maycalculate the capacitance using the area of each terminal of eachcapacitor, the distance between the two terminals of each capacitor, andthe dielectric constant of the material located between two terminals ofeach capacitor.

[0042] When the inductor 34 is added in parallel to the storagecapacitor 33, an inductor and capacitor interaction occurs, resulting ina LC circuit having a resonant frequency. Several additional variables(other than those in the previous paragraph) must be used to calculatethe charge time for the capacitor 33 in the presence of inductor 34. Theinductor 34 has an inductance (measured in henneries) that is calculatedusing a coil and core model. Such a model may be based on a phenomenoncalled the “skin effect” as described in “Fundamentals of Electronics”by E. Norman Lurch, John Wiley and Sons, Inc, Second Edition, 1971 atpage 236 in Chapter 9 (which chapter is incorporated by reference hereinin its entirety). For example, one may calculate inductance usingvarious parameters, such as size of the coil (e.g. area of surface 22 inFIG. 4), the volume and density of the material in the core, and thedielectric constant of the trap material, as would be apparent to theskilled artisan.

[0043] Once the inductance of the inductor 34 and the capacitance ofcapacitor 33 is calculated then the time constant of the LC circuitformed by the interaction between the storage capacitor 33 and theinductor 34 is found (e.g. using a Laplace transform of the type wellknown in the art). Next, one may compute the difference between thecharge time of capacitor 33 in the presence and absence of charges intrap material 37. This difference is used by sensor 56 to determinewhether or not a charge was stored in trap material 37 (e.g. whether ornot a bit 1 is stored in circuit 50 when used as a part of a memorycell).

[0044] Storage capacitor 33, inductor 34 and sense capacitor 55 togetherare represented, in circuit diagrams of one embodiment, by a singlesymbol 60 (FIG. 6). Such a symbol 60 may be used, for example, in aprogrammed computer by circuit modeling software for interpretinginstructions in hardware description languages, such as SPICE orVERILOG. Such software (which is normally stored in the memory of thecomputer) includes instructions to model a capacitor in the normalmanner, except that the capacitor charges and discharges significantlyfaster than (e.g. twice as fast or 10 times as fast as) a conventionalcapacitor of the same rating. The higher speed effectively models theinductive effect of the inductive storage capacitor represented bysymbol 60. One embodiment of the inductive storage capacitor is operatedat speeds above 1 GHz, which overcomes a prior art problem of speed andresponse time of conventional memory.

[0045] Therefore, in one embodiment, engineers that designmicroprocessors, digital signal processors, logic, or memory may usesuch a single symbol in a circuit diagram (which may be on paper or on acomputer screen, depending on the circumstances) to identify acombination of circuit elements that form an inductive storage capacitoras described herein. Thereafter, when the circuit is realized in asemiconductor wafer, an inductive storage capacitor is fabricated asdescribed elsewhere herein.

[0046] In one embodiment, symbol 60 has two parallel line segments 62and 63 (that represent a capacitor), and a spiral 61 (that represents aninductor) wrapped around the two parallel line segments 62 and 63 (whichmay be shown, for example, as vertical lines). Note that in theembodiment illustrated in FIG. 6, a capacitor symbol well known in theart and an inductor symbol well known in the art are overlapped, and anoptional rectangular box 66 is added to represent storage, thereby toform the new symbol 60. Optionally, the two symbols may be shownconnected, at one end, to a common line segment 69, which represents,for example, an input line to the device (for connection to a voltagesource). Note that in the embodiment illustrated in FIG. 6, a horizontalline 69 is shown connected to each of (1) line segment 62 and (2) spiral61.

[0047] Symbol 60 optionally has a third parallel line segment 64 that isshorter than the two parallel line segments 62 and 63. When present, thethird parallel line segment 64 is set apart from spiral 61. Also, symbol60 optionally has a box 66 (which represents trap material 37) locatedbetween the two parallel line segments 62 and 63. An output line 65 maybe connected to the third parallel line segment 64, when present.Although specific embodiments of symbol 60 are illustrated in FIG. 6,other such symbols will be apparent to the skilled artisan.

[0048] When voltage source 31 (FIG. 7) is applied to an input trace 25connected to a terminal 24 located at one end of surface 21 ofconductive sleeve 3, a number of electron waves 26A-26M (wherein A≦J≦M,M being the total number of waves) originate at terminal 24 and travelaround surface 21, as shown by waves 28A-28M (which represent waves26A-26M after a time delay), thereby to form a current flow. Althoughterminal 24 where electron waves originate is located at the end ofsurface 21 of sleeve 3, in other embodiments, terminal 24 is separatedby a distance from the end, as long as an inductive effect is present.As discussed elsewhere, the inductive effect must be sufficient to movefree electrons into trap material 37. The inductive effect arises fromthe flow of electrons along a path defined by physics, as they moveacross surface 21. This movement is defined by Boltzmann's principlewhich states that electron groups or waves vectors (momentum) move at avelocity and across the conductive surface generating an electromagneticforce (emf) that in turn creates an inductive field 23 (illustrated byflux lines 23A-23N).

[0049] The carrier flux or field strength that is created by waves28A-28M is calculated using Newton's Law of Motion. The electrons gainmomentum as they move across the surface 21 they use a sphericalparabolic path (as illustrated by waves 26A-26M and 28A-28M) followingthe laws of motion and follow the band structure of the material. Asmomentum is gained across the surface the field strength and directionare determined. The field strength and flux are a function of both thecapacitor and inductor resonant frequency. As the inductive field 23(FIG. 7) is built, the surface 21 collects electrons, and plug 4 has anopposite charge forming thereon. The free electrons migrate away fromsurface 22, toward the center of plug 4 and become resonant, e.g. atsurface 44. As this build up of charges occurs, surface 46 of element 45is also charging. As the charges collect on element 45, a voltage iscreated on element 45, and this voltage causes a current to startflowing through sensor 56.

[0050] In one embodiment, a dielectric material 410 (FIG. 8) betweenconductive sleeve 3 and plug 4 may be a single layer of dielectricmaterial (like silicon nitride Si₃N₄). Such a device 420 that has asingle dielectric layer still contains a capacitor and inductor asdescribed above, but does not have the ability to store a charge. Thisdevice operates at resonant frequency and is used in radio frequency(RF) circuits, e.g. for band pass or tuning filters used incommunication device. This design has advantages in that theinductor/capacitor is manufactured in a smaller element on the siliconwafer and requires less surface area than conventional RF circuits.

[0051]FIG. 9 shows a cross section of an inductive storage capacitor 100of the type described above, implemented in a via hole 101 formed in asemiconductor material 102 (such as raw silicon or in an epitaxiallayer). Inductive storage capacitor 100 includes a first layer 191 ofaluminum, which forms the conductive sleeve 3, and connected thereto isa trace 190. Inductive storage capacitor 100 also includes a trapmaterial 5 formed at an interface between a second layer 192 of asilicon (Si) dielectric material and a third layer 193 of silicondioxide (SiO₂). Therefore, trap material 5 of this implementation is asilicon—silicon dioxide (Si—SiO₂) interface. Inductive storage capacitor100 also includes a fourth layer 194 of silicon nitride (Si₃N₄) thatprovides a dielectric of high value for the storage capacitor andinductor elements. Inductive storage capacitor 100 further includes afifth material which is a conductive material like aluminum or copperand which forms a plug 195 that is located inside the via hole 101.

[0052] Depending on the implementation, inductive storage capacitor 100also includes a dielectric material 196 located over plug 195, to formthe dielectric element of sense capacitor 48. Note that dielectricmaterial 196 can be formed of any semiconductor material commonly usedfor insulation such as silicon and silicon oxide, although in oneembodiment material 196 includes silicon nitride (Si₃N₄) which ensuresthat junctions formed therein have better thermal conductivity, andbetter adhesion than other semiconductor materials. Located overdielectric material 196 is a layer of conductive material 197, likealuminum or other conductive material, which forms sense capacitor 55.This material 197 is then connected to a sensor through a lead 198. Inone or more alternative implementations, materials 196-198 are not usedand instead, trace 190 is connected to a voltage source 31 and also to asensor 36 as described above.

[0053] In one implementation illustrated in FIG. 9, a device (thatincludes inductive storage capacitor 100) has, attached to conductivesleeve 3, a floor 91 also formed of first layer 191. Floor 91 overlapsat least a region of plug 195 when viewed in a direction perpendicularto plug 195. The combination of sleeve 3 and floor 91 is also referredto as a “cup-shaped element”, and in one embodiment has an aspect ratioin the range of 1 to 5 although other aspect ratios may be used in otherembodiments.

[0054] Conductive layer 197 together with sleeve 3 and floor 91substantially enclose plug 195. So, any charge that may be stored in theregion (also called “storage tunnel”) between plug 195 and suchsurrounding elements is less likely to be affected by alpha particlesthan in prior art devices, such as flash memory. At the same time, thestorage tunnel holds a charge in a non-volatile manner, even when nopower is supplied to the device as described elsewhere.

[0055] Instead of floor 91, a roof 290 may be attached to capacitor 100as illustrated in FIGS. 26-28. Roof 290 (FIG. 28) is located at the topof the sleeve (and is also called a “cap”). Note that in anotherimplementation, such a structure does not have a cap or a cup, i.e. hasonly the sleeve. Referring back to FIG. 9, floor 91 which may be anartifact of a manufacturing process, may be eliminated as discussedbelow in reference to FIG. 17, thereby to ensure that the resultantdevice effectively functions as an inductive storage capacitor 100.

[0056] Circuit elements of inductive storage capacitor 100 are shownoverlayed onto a cross-sectional view in FIG. 10. The interaction of thecoupled devices creates the equivalent circuit to the circuit in FIG. 5.The input lead 190 is connected to layer 191 (FIG. 10) which forms afirst terminal 203 of a storage capacitor 33. Conductive sleeve 3 alsoforms a coil of the inductor 34. Plug 195 forms a core of the inductor34. During operation, inductor 34 creates an electrical field 204 aroundthe plug 195. Plug 195 forms an electrical path 209 from the secondterminal 207 of storage capacitor 33 to a terminal 208 of the sensecapacitor 55. Conductive material 197 forms a second terminal 206 ofsense capacitor 55, which is connected by lead 198 to a sensor.

[0057] The storage of electrons in inductive storage capacitor 100occurs at an interface 214 (FIG. 11) in trap material 5 (FIG. 1), wherethe inductive field 204 works with the storage capacitor 33 to cause thegeneration of electron hole pairs to occur in a phenomenon known as‘Trap-to-Band Tunneling (TBT)’. As the input voltage is applied, theelectron waves move around first layer 191, thereby to form an inductivefield 204. Storage capacitor 33 causes electron to accumulate alonginterface 214 formed between second layer 192 and third layer 193.Another interface 215 formed between third layer 193 and fourth layer194 also provides an electron-trapping interface, although not as strongas interface 214. Fourth layer 194 provides a high dialectic material tohold the electrons at interface 215, and to stop the flow of electronsinto plug 195. When the voltage level on first layer 191 reaches amaximum, the inductive field 204 collapses causing the electrons to betrapped in trap material 5.

[0058] In one embodiment, trap material 5 at interface 214 (FIG. 12) ismade up of silicon atoms 220A-220Z (Z being the number of siliconatoms), and oxygen atoms 221A-221X (X being the number of oxygen atoms),wherein X<Z. Although silicon and oxygen atoms were just described inone example, trap material 5 is any material in an amorphous (andvitreous, meaning that the atomic structure is ordered only over shortdistances) form having free (or dangling) electron bonds. Anotherembodiment uses trap material 5 in the form of α—quartz which features aperfectly ordered arrangement of Si atoms located at the center oftetrahedral, and oxygen atoms at the vertexes. Each oxygen atom occupiesa bridging location and forms two chemical bonds with Si atoms belongingto adjacent tetrahedral.

[0059] In the example illustrated in FIG. 12, trap material 5 hasdangling electron bonds 222A-222P, and also has stretchedsilicon-to-silicon Si—Si bonds 223A-223L. The dangling electron bonds222A-222P are randomly distributed, and allow for electrons to rapidlyexchange charges, also known as ‘fast surface states,’ and can becomehole traps as they can capture and release electron carriers. Hole trapscan be of two types: acceptor traps (that are empty holes) and donortraps (that are occupied holes).

[0060] When acceptor traps are empty or neutral and a field is generatedand electrons start moving, these traps are filled with negativelycharged electrons and become donor traps, which are neutral whenoccupied (and are positively charged). Depending on the implementation,such traps may be filled in, e.g. 327 picoseconds. Storage capacitor 33and inductor 34 (FIG. 5) cause an electrical field 204 (FIG. 12) alonginterface 214 to expand and collapse, which in turn causes electrons tomove into and become trapped in this interface 214. As the electricalfield 204 expands the amount of work or kinetic energy used to move theelectrons into the traps is measured by monitoring voltage or currentproduced by the sense capacitor 55 (FIG. 5). If interface 214 (alsocalled “storage tunnel”) already contains trapped electrons, then moreelectrons will be free to migrate to the sense capacitor 55 and theoutput of the sense capacitor 55 will more closely follow the source 31of the input voltage. If interface 214 does not contain trappedelectrons then most of the kinetic energy will be used to move electronsto interface 214 (FIG. 12) and trap them. The output charge of sensecapacitor 55 will be delayed until interface 214 reaches a full orequilateral state.

[0061] In one embodiment of the device, a via hole 101 (FIG. 13) iscreated in semiconductor material 102 (such as a wafer of silicon, orgermanium) that may be present in a semiconductor substrate 103. In oneexample a circular three-micron wide by 10 microns deep hole 101 with anaspect ratio of 3 to 10 is created in semiconductor substrate 103. Theshape of via hole 101 in cross-section is circular, elliptical, square,triangular or any other shape that allows a conductive sleeve 3 (FIG.14) to be built separate and distinct from a core 195 (to form aninductor when a trace is coupled to one end of the conductive sleeve 3).Moreover, as noted elsewhere, the sidewall of via hole 101 can beslanted, so that core 195 has the shape of a frustrum of a cone. Thewidth W (FIG. 13) of via hole 101 is sufficiently large enough to allowhole 101 to accommodate at least a core, trapping material surroundingthe core, and a conductive sleeve surrounding the trapping material (asdiscussed above in reference to FIG. 1), each of uniform thickness asdiscussed below.

[0062] As process technology evolves the aspect ratio of height to widthis changed to allow for the creation of devices of different resonantfrequencies. The ratio is determined by the design of the inductivestorage capacitor, because the capacitance and the inductance depend onthe speed of operation of the device (which in turn is determined by aresonant frequency).

[0063] Thereafter, a layer 104 (FIG. 14) of a conductive material, likealuminum or copper, is formed in hole 101. Conductive sleeve 3 is formedas a sidewall in contact with a surface of via hole 101. Depending onthe manufacturing process, the just-described sidewall is perpendicularto the surface 105 of semiconductor substrate 103, but may be angled toreduce faseting and trenching of layers that are to be deposited in thespace defined by conductive sleeve 3. An additional step may beperformed, to deposit a dielectric material between a surface of viahole 101 and conductive sleeve 3 to protect operation of sleeve 191 inthe presence of impurities in substrate 102.

[0064] A layer 104 of electrically conductive material (like aluminum,copper, platinum, titanium, or polysilicon) is deposited (FIG. 14) intothe via hole 101 using a PVD processing. In one embodiment the sleevethickness T, e.g. of 10 angstroms of conductive aluminum material wasused. A Rapid Thermal Process (RTP) may be used to anneal the surface 21if the surface 21 contains spikes, e.g. created by the physical vapordeposition (PVD) process.

[0065] In one embodiment, a second layer 192 (FIG. 15) is formed (e.g.of silicon (Si)) on surface 21 of conductive layer 191. Second layer 192is applied using, e.g. chemical vapor deposition (CVD) process todeposit 30 angstroms (or 3 μm) thick silicon. Next a third layer 193(FIG. 16) is formed, e.g. silicon dioxide (SiO₂) is deposited at athickness of 100 angstroms (or 10 μm) over second layer 192 using a CVDprocess creating trap material 5 (e.g. a silicon-silicon dioxideinterface junction). A fourth layer 194 (FIG. 17) is formed, e.g. ofsilicon nitride (Si₃N₄) which has a high dielectric value is thendeposited using a CVD process, over third layer 193 at a thickness of 30angstroms (or 3 μm). After formation of layer 194, a hole is etched infloor 91, through layers 191-194, in one embodiment to obtain a desiredresonant frequency, inductance or capacitance, or to eliminate secondaryeffects. Next, a plug 4 (FIG. 18) of a conductive material is formedusing a PVD process into the via hole 101 to fill the via hole.

[0066] The thickness T of the sleeve and the area of surface 21 (ofsleeve 191) determine the sheet resistance, which can be used (asdiscussed above in reference to FIGS. 1 and 2) to calculate theinductance and the capacitance of inductive storage capacitor 100. Suchvalues are used to tune the device to operate at any desired resonantfrequency. The resistance and capacitance are used to compute an RCtransmission line value, and the circuit delay is calculated therefrom,to determine the proper timing for reading the charge status of thedevice to determine if the trap material contains a charge. The size(diameter and height) of plug 4 determines the area of surface 180, thatin turn is used to calculate the capacitance. The density of plug 4 isused to calculate the inductance. The area of an end surface 181 of plug4 is determined to calculate the capacitance of a sense capacitor 48. Bychanging the height and diameter of the core (formed by plug 4)different values are achieved for each of the inductance, and the twocapacitances, to tune the device for a specific resonant frequency forthe operation of the device.

[0067] In one embodiment, a dielectric layer 196, e.g. of siliconnitride (Si₃N₄) (FIG. 19) of high dielectric value, is then depositedusing a CVD process, over plug 4 at a thickness of 200 angstroms or 20μm. A conductive layer 197 (FIG. 20), e.g. of polysilicon (or otherconductive material like aluminum) is deposited using a CVD or PVDprocess over the dielectric layer 196 to form sense capacitor 48. Thesurface area of a portion of layer 197 used to form sense capacitor 48is calculated to determine the capacitance of sense capacitor 48.

[0068] Although other cross-sections may be used in other embodiments,in one embodiment the device illustrated in FIG. 20 has a circularcross-section (FIG. 21) when viewed along the section line AA (FIG. 20).Specifically, each of layers 191-194 have circular cross-sections andform concentric circles surrounding one another, with layer 191 beingthe outermost layer. Innermost layer 194 surrounds core 195 that alsohas a circular cross-section.

[0069] In one embodiment, during operation, inductive storage capacitor100 is charged and discharged as illustrated in FIGS. 22-25. FIG. 22shows the timing sequence for reading inductive storage capacitor 100that has a discharged state initially at time t0 (shown on the X axis),and for writing into inductive storage capacitor 100 a charged state bytime t4. Specifically, curves 321-324 represent, along the Y axis theinput voltage Vi, inductive flux F, stored charge Cs, and sensor voltageVs respectively.

[0070] At time t0, input voltage Vi, inductive flux F, stored charge Cs,and sensor voltage Vs are all zero. At time t0 a signal of voltage Vmax(e.g. 3V) is applied to trace 25 (FIG. 4), and in response the voltageat terminal 24 starts to rise as shown by segment 321 a of curve 321until voltage Vmax is reached at time t1. Simultaneously, avoltage-induced inductive flux F is formed as shown by segment 322 a.This inductive field 23 (FIG. 4) is present between the storagecapacitor elements 21 and 22, and causes free electrons to collect intrap material 5 (FIG. 1), as shown by segment 323 a of curve 323. Asboth capacitor 29 (FIG. 2) charges and inductive field 23 increases, theelectron population in trap material 5 increases. Therefore, at time t1,a charge Cl is stored in trap material 5. Charge C1 is smaller thananother charge C2 that denotes a charged state.

[0071] Simultaneously, in the time period t0-t1, sense capacitor 48starts to charge slowly as shown by segment 324 a because most of theenergy injected into the inductive storage capacitor 100 is used to movefree electrons into storage tunnel formed at interface 214. When thevoltage level Vi on the storage capacitor 29 is equal to the supplyvoltage Vmax at time t1 then the inductive field 23 collapses as shownby segment 322 b.

[0072] Sense capacitor 48 has an output voltage Vs as shown by segment324 a, and this voltage is tested at time t1 to find out if the energyinjected into the inductive storage capacitor 100 has caused the outputvoltage Vs to rise above a threshold Vthresh. In this example, theoutput voltage Vs is below the threshold Vthresh, and therefore thestate of the inductive storage capacitor 100 is discharged. Instead ofhaving just two states of charged and discharged as described above inreference to FIG. 22, an inductive storage capacitor 100 can have one ormore intermediate states, e.g. have a total of four states (indicatingfour levels of stored charge), if the threshold Vthresh is reached atdifferent time intervals from start time t0 as discussed below inreference to FIG. 25. For examples of implementing such multiple statesusing a single storage capacitor, see Chapter 6 of the book entitled“Flash Memories” by Paolo Cappelletti et al. Kluwer Academic Publishers,1999, which chapter is incorporated by reference herein in its entirety.

[0073] As inductive field 23 collapses as shown by segment 322 b anumber of free electrons (representing additional charge C2-C1) entertrap material 5 as shown by segment 323 b (between times t1 and t2) andthe opposite charges will rapidly collect on sense capacitor 48 as shownby segment 324 b (between times t1 and t2). This rapid movement ofcharges (as shown by segment 323 b) causes a voltage and current spikeas shown by segments 324 b and 324 c to occur on the output of sensecapacitor 48.

[0074] In this embodiment, the output voltage Vs of sense capacitor 55is monitored by sensor 56 a second time, at time t2, in addition to themonitoring at time t1 as discussed above, to verify that storage ofcharge C2 (indicative of the read process) has occurred, by checkingthat Vs has exceeded Vthresh. If inductive storage capacitor 100 isdefective, this test fails, thereby to identify a failed device.Therefore, inductive storage capacitor 100 has built in error checkingof the type not available in prior art storage capacitors.

[0075] If inductive storage capacitor 100 is to be charged after theread process, then the input terminal 24 is disconnected from thevoltage supply 31 (FIG. 5) as shown by segment 321 d, because a chargehas been already stored as described above in reference to FIG. 22.Because the dielectrics are not perfect, some leakage of storagecapacitor 100 occurs slowly over time (depending on the dielectricleakage) as shown by segment 321 d. This slow decay occurs after timet3, and is insufficient to cause a significant inductive field to beformed (field sufficiently significant to discharge the charge C2 tozero coulombs over the life of the device, e.g. 1 year).

[0076] If inductive storage capacitor 100 happens to contain a storedcharge prior to the read process (as illustrated by segment 333 a inFIG. 23), then during time period t0-t1, voltage Vs (see segment 334 a)at the output trace 198 (FIG. 9) of sense capacitor 55 follows thevoltage Vi (see segment 321 a) presented at input terminal 24. In thiscase, output voltage Vs exceeds the threshold voltage Vthresh at a timet0 a, prior to time t1. Time t0 a being smaller than time t1 indicatesto sensor 56 that inductive storage capacitor 100 contained a storedcharge prior to the read process. In all other respects, inductivestorage capacitor 100 operates in the same manner as described above inreference to FIG. 22, including operation of sense capacitor 48 at timet2 to verify that a charge has been stored.

[0077] To store a discharged state in inductive storage capacitor 100,the input terminal of the storage capacitor 29 is grounded (see segment341 c in FIG. 24). Storage capacitor 29 is discharged and oppositepolarity inductive field (shown negative in FIG. 24) is generated (seesegment 342 c). When storage capacitor 29 has completely discharged (seesegment 341 d) and is at or below ground reference (see time periodt3-t4) then the inductive field 23 (see segment 342 d) collapses toreach zero at time t4. During time period t2-t3, the opposite polarityinductive field starts to empty the stored charge in trap material 5 (asshown by segment 343 c). Between times t3 and t4, the collapse ofinductive field 23 forces the electrons in trap material 5 to beattracted to surface 44 (FIG. 4) and trap material 5 becomes empty (seesegment 343 d) at time t4. During time period t2-t3, the charge in sensecapacitor 55 also decays (see segment 344 c) in response to the loss ofcharge in trap material 5, and when the storage capacitor 29 hasdischarged (at time t4) the sense capacitor 55 will have also discharged(see segment 344 d). During this storage process as well, sensecapacitor 48 may verify that a discharge occurred, e.g. if the voltageat output trace 198 of sense capacitor 55 falls to a negative thresholdVn at time t4 (e.g. a −3 volt spike).

[0078] In one embodiment, input terminal 24 of storage capacitor 29 isgrounded (see segment 351 c in FIG. 25), and inductive storage capacitor100 operates as discussed above in reference to FIG. 24, except for ashorter duration than t2-t4. Specifically, the duration is selected toimplement one or more partially charged states for inductive storagecapacitor 100. For example, to implement two states in addition to thecharged and discharged states, input terminal 24 is decoupled from theground reference (e.g. allowed to float) after the respective durationsTx and Ty, as illustrated by segments 71-72, and therefore storagecapacitor 29 remains partially charged as illustrated by segments 73-74.The partially stored charge in inductive storage capacitor 100 is readat durations Tx and Ty that are identical to the corresponding durationsused in storing the partial charge, because the device charges anddischarges at the same rate due to the resonant frequency. Such multiplestates of inductive storage capacitor 100 are used to store multiplebits of data.

[0079] In another embodiment (FIG. 26A) the inductive storage capacitor360 is constructed on top of a semicondutor wafer instead of inside avia hole. In this example inductive storage capacitor 360 has beencreated upside down in the same manner as that described above inreference to FIGS. 13-20 except for the following differences. Theprocessing steps are reversed with construction of the inductive storagecapacitor 360 starting with a conductive layer 197 that is used to formsense capacitor 48 (FIG. 4). Specifically, conductive layer 197 isdeposited using either a metal or polysilicon. Next, a dielectric layer196 is deposited on conductive layer 197 using a CVD process.Thereafter, plug 195 (e.g. metal) is deposited followed by fourth layer194 (e.g. silicon nitride (Si₃N₄)). The third layer 193 (e.g. silicondioxide) and second layer 192 (e.g. silicon) are then added. Then firstlayer 191 (e.g. metal that forms a sleeve or cup) is deposited andconnected to the circuit to form inductive storage capacitor 360.

[0080] Note that several of the just-described acts can be performedafter a thick dielectric is deposited and then a via hole created, e.g.layers 192-195 are deposited in the via hole. Also, a transistor 363(FIG. 26B) can be built first, followed by formation of inductivestorage capacitor 360 as described above. Specifically, drain 367,source 368 and base 369 are initially implanted into a substrate 399,followed by formation of interconnects 364 and 366 on a surface of thesubstrate 399. Next, a gate oxide 362 is deposited and a gate junction365 is also deposited, followed by more oxide 362. Thereafter, via 198is formed in contact with gate junction 365, followed by formation oflayers 197-191 as described above.

[0081] In another embodiment (FIG. 27) the inductive storage capacitor360 is formed upside down over a transistor (as described above inreference to FIG. 26A), but the transistor's control gate 365 and via198 are eliminated. The function of gate 365 is performed by conductivelayer 197 of sense capacitor 55. In yet another embodiment (FIG. 28) theinductive storage capacitor is formed as described above in reference toFIG. 27, but conductive layer 197 of sense capacitor 55 is eliminated.The function of gate 365 (FIG. 26) is performed by plug 195. In stillanother embodiment, a roof 290 (FIG. 28) is eliminated (e.g. etched awayor not deposited) thereby to form a sleeve 191 instead of a cup (FIG.29).

[0082] In yet another embodiment, a plug 195 (of any inductive storagecapacitor as described herein) is made hollow, e.g. has a hole 401 (FIG.30) at the center, and a material 402 may be deposited in such a hole401. Material 402 can be formed in an amorphous (and vitreous, meaningthat the atomic structure is ordered only over short distances) form tocreate free or dangling electron bonds, same as trap material 5.Therefore, material 402 forms an additional storage tunnel (of the typedescribed above in reference to trap material 5). The two storagetunnels in such an inductive storage capacitor act in concert to workbetter than a single storage tunnel. When two storage tunnels are used,a sense capacitor may be eliminated to prevent a charge in the storagetunnel in the plug from generating a false signal in the sensecapacitor.

[0083] Note that the just-described additional storage tunnel canreplace the storage tunnel at interface 214 (FIG. 12), for example iftrap material 5 is not present between sleeve 3 and plug 4 (FIG. 1). Insuch a case, trap material 5 is replaced with any dielectric material.

[0084] In alternative embodiments, material 402 can be any material thatis responsive to an inductive field 23. In one implementation, material402 is a ferroelectric material that has a perovskite crystal structuredescribed by the general chemical formula ABO₃, where A and B are largeand small cations respectively. Therefore, any material that hasparaelectric, pyroelectric, piezoelectric, or ferroelectric property canbe embedded in plug 195. Examples of ferroelectric material that can beembedded in plug 195 include Pb,Zr,TiO₃ (PZT); Pb,La,TiO₃ (PLT);Pb,La,Zr,TiO₃ (PLZT); BaTiO₃; Pb,Mg,NbO₃ (PMN); Pb,Mg,NbO₃—PbTiO₃(PMNPT); SrTiO₃ to name a few.

[0085] A plug 195 that has embedded therein a piezoelectric material mayalso be used with an inductive storage capacitor that is devoid of trapmaterial 5. In such a case, use of a piezoelectric material in plug 195has the advantage of being able to control the direction and/ormodulation of a beam of light or electrons or electromagnetic energy.Therefore, such a device can be used with a source of light (such as anLED or TFT) built into a semiconductor substrate, e.g. instead of atransistor as described above in reference to FIGS. 26-29.

[0086] In one embodiment, an inductive storage capacitor of the typedescribed herein is used as a storage element 50 (FIG. 31) in a memorycell 501 that may include a switch 505 coupled to storage element 50 bya conductive trace 25. Switch 505, when operated by a control signal ona line 506, couples a trace 500 (that carries a signal of voltage Vmax)to an input terminal of storage element 50 (via trace 25). Memory cell501 may be operated by a read/write switch 502 that provides the controlsignal on line 506. Memory cell 501 is coupled by an output trace 507 toa sensor 56 (as described above in reference to FIG. 5).

[0087] In one implementation, switch 505 is implemented by an NMOStransistor 605 (FIG. 32) having a gate connected to trace 506 (that isconnected to read/write switch 502 as discussed above), and storageelement 50 is implemented by inductive storage capacitor 100. Transistor605 is turned on during the read cycle, and the output of the inductivestorage capacitor 100 is read by the sensor 56 (that is implemented by aCMOS transistor 604).

[0088] In one embodiment, the following signals (wherein 1 represents acharged state and 0 represents a discharged state) are present at theinput/output terminals of memory cell 501. Input line Read/Write MemoryCell Memory Cell 500 line 506 state output 507 Read 0 1 1 Discharged  0Read 1 1 1 Charged  1 Write 0 0 1 Discharged −1 Write 1 float 0 Charged 0

[0089] Specifically, in a read operation, input line 500 and read/writeline 506 both carry a high signal, and a stored charge (either 0 or 1)is supplied on output line 507. Note that at the end of each readoperation, memory cell 501 has been charged. In an operation to write a0, input line 500 carries 0 and read/write line 506 carries a highsignal, and memory cell 501 is discharged to a voltage of zero. In anoperation to write a 1, input line 500 floats and read/write line 506carries a low signal, and memory cell 501 stays charged.

[0090] In one embodiment, a memory array 340 (FIG. 33) uses a number ofinductive storage capacitors (of the type described herein), eachcoupled to receive a signal of voltage Vmax from a respectivetransistor, thereby to form a two-dimensional array of memory cells 100a-100 z. An address bus 341 (e.g. coupled to a CPU) provides inputsignals for an address decoder 342. In response to the input signals,address decoder 342 selects one of several select lines 343 a through343 n to access a row 350 a of memory cells 100 a through 100 g locatedin the array. An active signal on select line 343 a from decoder 342,causes voltage source 344 to provide signals to timing control circuit354 that in turn supplies a signal to transistor 345 a.

[0091] Transistor 345 a passes the signal from timing control circuit354, through a line 350 a, to each of memory cells 100 a-100 g.Transistors 346 a-346 g in the respective memory cells 100 a-100 g havetheir gates coupled via their respective transistors 348 a-348 g to adata decoder 353. Data decoder 353 receives a control signal (e.g. fromtiming control circuit 354) to turn on transistors 346 a-346 g during aread operation. When turned on, transistors 346 a-346 g pass the signalof voltage Vmax from voltage source 344 to their respective inductivestorage capacitors (not labeled). In response, inductive storagecapacitors provide their stored charges to output lines 373 a-373 g thatare coupled to the respective sensors 349 a-349 g. Sensors 349 a-349 gare coupled to a latch 356, that in turn provides the latched signals toan output data bus 357.

[0092] During a write operation, address decoder 342 operates in thesame manner as that discussed above for the read operation. The data tobe stored is received on an input data bus 352, and is decoded in datadecoder 353. Data decoder 353 operates transistors 348 a-348 g to driveappropriate signals to the respective inductive storage capacitors, towrite a zero (or discharged state) or one (or charged state). When azero (or 1) is set then the column transistor 348 a-348 g is turned on(or off) to allow the voltage source 344 to discharge (or stay charged)memory cells 100 a-100 g.

[0093] To generate signals for transistors 348 a-348 g, data decoder 353inverts the data received on data input bus 352, because a previous readoperation has left memory cells 100 a-100 g in a charged state, and datadecoder 353 must determine which cells must be discharged (to reflectthe data received on bus 352). As a read operation always precedes awrite operation, decoder 353 must invert the data signal.

[0094] Furthermore, as a read operation results in charged state of thememory cells 100 a-100 g, all data stored in these cells is no longerleft therein, thereby resulting in a destructive read. Therefore, latch356 may be coupled to transistors 346 a-346 g which pass the signal ofvoltage Vmax from voltage source 344 to their respective inductivestorage capacitors (not labeled), so that the just-read data isrewritten (at the end of a read operation) into memory cells 100 a-100g. Note that any addressing circuitry that operates with destructiveread memory cells can be used, e.g. see U.S. Pat. No. 4,153,934 that isincorporated by reference herein in its entirety.

[0095] Numerous modifications and adaptations of the embodiments,implementations and examples described herein will be apparent to theskilled artisan in view of the disclosure. For example, an inductivecapacitor of the type described herein, but devoid of the trap material,is used in one embodiment of a radio-frequency circuit (such as an RFdetector) as an LC filter. Such an LC filter has the advantage ofeliminating the need for an external filter, and takes less real estateon the die than a conventional LC filter in which the inductor is formedseparate and distinct from the capacitor. Furthermore, although in someembodiments, certain surfaces are flat, or cylindrical, or parallel, orcoaxial to one another, in other embodiments, other surfaces may justapproximate such surfaces to within 10% variation in a measure of therespective properties (such as two surfaces with 10% variation indistance therebetween are considered approximately parallel, and asurface is considered approximately cylindrical if it fits within twoconcentric cylinders with the smaller cylinder having 90% of the volumeof the larger cylinder), depending on manufacturing constraints.

[0096] Numerous such modifications and adaptations are encompassed bythe attached claims.

1. A device comprising: a first element; a second element at leastpartially surrounding the first element and physically separated fromthe first element; and a material having a plurality of dangling bonds,said material being located between said first element and said secondelement.
 2. The device of claim 1 further comprising: a semiconductorsubstrate; wherein each of the first element, the second element and thematerial are supported by the semiconductor substrate, and the materialincludes a semiconductor material.
 3. The device of claim 1 wherein thesecond element surrounds a majority of a surface of the first element.4. The device of claim 1 wherein the first element includes anelectrical conductive material.
 5. The device of claim 1 wherein thesecond element includes an electrical conductive material.
 6. The deviceof claim 1 wherein the first element is at least approximatelycylindrical in shape.
 7. The device of claim 1 further comprising: athird element physically separated from each of the first element andthe second element, the third element being located transverse to eachof a first axis of the first element and a second axis of the secondelement.
 8. The device of claim 7 wherein the first element and thethird element form a capacitor.
 9. The device of claim 7 wherein thefirst element has a first end facing the third element, the first endbeing at least approximately flat.
 10. The device of claim 9 wherein thethird element has a surface at least approximately parallel to the firstend.
 11. The device of claim 7 wherein each of the second element andthe third element include a common electrical conductive material. 12.The device of claim 7 wherein the second element includes one electricalconductive material and the third element includes another electricalconductive material.
 13. The device of claim 7 wherein an electricalcharge can be sensed in the third element.
 14. The device of claim 1wherein the first element includes a trap material surrounded by anelectrically conductive material.
 15. The device of claim 1 wherein thefirst element and the second element form a capacitor.
 16. The device ofclaim 1 wherein the first element and the second element form a firstcapacitor and the first element and the third element form a sensecapacitor, wherein the first capacitor and the sense capacitor arecoupled in series.
 17. The device of claim 1 wherein the first elementand the second element form an inductor, with the first element actingas a core and the second element acting as a coil.
 18. The device ofclaim 1 wherein the first element generates an electrical charge inresponse to applying power to the second element.
 19. The device ofclaim 1 wherein: the first element is cylindrical in shape with at leastone flat end; the first element and the second element are conductive; amaterial between the first element and the second element is at leastsubstantially dielectric; the third element is at least substantiallyparallel to the flat end of the first element; and another materialbetween the first element and the third element is at leastsubstantially dielectric.
 20. A device comprising: an annular elementlocated in a via hole of a semiconductor material; a plug located in thevia hole and surrounded at least partially by but isolated from theannular element; and another element facing one end of the plug.
 21. Thedevice of claim 20 wherein the plug is at least approximatelycylindrical in shape.
 22. The device of claim 21 wherein an axis of theannular element is at least approximately coaxial with an axis of theplug.
 23. The device of claim 20 wherein said another element isconnected to the annular element and is isolated from the plug, and thedevice further includes yet another element facing another end of theplug.
 24. The device of claim 23 wherein the only connection of saidanother element to a voltage source is through the annular element. 25.The device of claim 20 wherein: said another element is at leastapproximately planar and is hereinafter referred to as “end element”;and said end element is isolated from each of the plug and the annularelement.
 26. The device of claim 25 further including yet anotherelement located transverse to and connected to the annular element,wherein said elements at least partially enclose the plug.
 27. A devicecomprising: an element located in a via hole of a semiconductormaterial; and a core located in the via hole and separated from but atleast partially surrounded by the element.
 28. The device of claim 27wherein when viewed in a direction perpendicular to the core: a portionof the element overlaps at least a region of the core; and anotherportion of the element surrounds the core.
 29. The device of claim 27wherein the element is hereinafter “first element” and the devicefurther comprises: a second element separated from the core andoverlapping at least a region of the core when viewed in a directionperpendicular to the core.
 30. The device of claim 29 wherein the firstelement is connected to a first conductor for carrying a first voltage,the second element is connected to a second conductor for carrying asecond voltage, and the core is not connected to any conductor.
 31. Amultilayered structure comprising: a cup-shaped element defining aninterior volume; and a core located in the interior volume and separatedfrom but surrounded by a first wall of the cup-shaped element, one endof the core facing a second wall of the cup-shaped element; wherein saidsecond wall is transverse to and connected to said first wall.
 32. Thedevice of claim 31 further comprising: an electrode separated from eachof the core and the cup-shaped element, the electrode facing another endof the core.
 33. The device of claim 32 wherein: the electrode and thecup-shaped element substantially enclose the core.
 34. The device ofclaim 32 further comprising: a dielectric element formed of asemiconductor material and located between the core and the electrode.35. The device of claim 31 further comprising: a dielectric elementformed of a semiconductor material and located between the cup-shapedelement and the core.
 36. A circuit comprising: a capacitor; an inductorcoupled in parallel to said capacitor; and a dielectric material locatedinside said capacitor, said dielectric material having a plurality oftraps.
 37. The circuit of claim 36 wherein: the inductor is in contactwith the dielectric material.
 38. The circuit of claim 36 wherein: theinductor is adjacent to the dielectric material.
 39. The circuit ofclaim 36 wherein: during operation of said circuit said inductorgenerates a field passing through said dielectric material.
 40. Thecircuit of claim 36 further comprising: a sensor coupled to saidcapacitor.
 41. The circuit of claim 40 wherein: said capacitor and saidinductor are coupled to a common terminal; said sensor is coupled tosaid common terminal; and a voltage source is coupled to said commonterminal.
 42. The circuit of claim 36 wherein said capacitor ishereinafter “first capacitor,” and the circuit further comprises: asecond capacitor in series with said first capacitor.
 43. The circuit ofclaim 42 wherein: said dielectric material is not present inside saidsecond capacitor.
 44. The circuit of claim 42 further comprising: asensor coupled to said second capacitor.
 45. The circuit of claim 44wherein: a voltage source is coupled to a terminal of said firstcapacitor; and said sensor is coupled to a terminal of said secondcapacitor.
 46. A method comprising: forming a via hole in asemiconductor material; forming a first layer of conductive materialinside the via hole; forming a second layer of insulative material overthe first layer, the second layer defining an interior volume; forming athird layer of trap material in said interior volume; forming a fourthlayer of insulative material outside said via hole; and forming a fifthlayer of conductive material over the fourth layer.
 47. The method ofclaim 46 wherein: the third layer fills the interior volume; the thirdlayer contacts the second layer; and the third layer contacts the fourthlayer.
 48. A method comprising: forming a first layer of conductivematerial in the shape of a column, over a semiconductor material;forming a second layer of insulative material over the first layer;forming a fourth layer of insulative material over the second layerwhile simultaneously forming a third layer of trap material at aninterface between the second layer and the fourth layer; and forming afifth layer of conductive material over the fourth layer.
 49. A computercomprising: a monitor displaying a symbol, the symbol including: twoparallel line segments; and a spiral wrapped around the two parallelline segments; and a memory encoded with software that simulates acapacitor and inductor combination represented by the symbol.
 50. Amethod of forming a circuit diagram, the method comprising: drawing twoparallel line segments and a spiral wrapped around the two parallel linesegments to form a symbol; drawing a symbol of a circuit elementselected from a group consisting of a transistor and a resistor; anddrawing a line connecting the circuit element and the symbol.
 51. Themethod of claim 50 further comprising: drawing a rectangle between thetwo parallel line segments.